The present invention relates to a semiconductor device including a reservoir capacitor and a method of manufacturing the same, and more particularly, to a semiconductor device capable of substantially preventing a capacity of a reservoir capacitor from being reduced and a method of manufacturing the same.
A semiconductor memory device includes a cell region including a plurality of unit cells and a peripheral region including components which control a data transmission and a power supply, etc. The cell region includes the plurality of unit cells each of which comprised of a capacitor and a transistor. The capacitor is used to temporality store data, and the transistor is used to transfer data between the capacitor and a bit line in response to a control signal input through a word line by using a semiconductor property which the conductivity thereof varies according to a circumstance. The peripheral region includes input/output pads and data input/output lines for transferring data and an internal voltage circuit for supplying various voltages to internal circuits of the semiconductor memory device.
The semiconductor memory device includes reservoir capacitors in the peripheral region besides the capacitors comprising of the unit cells. Herein, the reservoir capacitor is included in the driving circuit of the peripheral region of the semiconductor memory device and stores electrons corresponding to voltages Vpp, Vblp, Vbb and Vint generated inside the semiconductor memory device to supply the stable power to the internal circuits of the semiconductor memory device. The reservoir capacitor may have large capacitance so as to supply a stable DC voltage.
The capacitance of a capacitor is proportional to a dimension of a capacitor electrode. That is, the larger the capacitor, the greater the capacitance. However, as an integration degree of the semiconductor memory device is increased, the dimension to be occupied by the capacitor is reduced. In particular, although the capacitor having a large capacitance is demanded in the cell region so as to store data for a long time, an area assigned to the cell capacitor is reduced much more, so that a capacitor having a 3-dimensional structure (e.g., a cylinder structure) is introduced to implement a capacitor having large capacitance in a small dimension. Meanwhile, the increase in integration degree in the peripheral region including the reservoir capacitor is lower than that in the cell region. Therefore, a capacitor having larger capacitance can be more readily fabricated in the peripheral region compared with in the cell region.
The reservoir capacitor included in the peripheral region of the conventional semiconductor memory device has been formed of a MOS capacitor of a planar type. This is because the area assigned to the capacitor is wide enough, and its fabrication process can be simplified by employing a MOS transistor formation process without adding processes required for fabricating the reservoir capacitor included in the peripheral region. Therefore, the source and drain regions of the MOS capacitor are electrically coupled to each other to perform the same function as the capacitor. Electrodes in the MOS capacitor are formed of a silicon layer of a semiconductor substrate and a polysilicon layer.
Recently, as a design rule is scaled down below 50 nm, the integration degree in the peripheral region of the semiconductor memory device gets higher. According to this, the dimension of the MOS capacitor occupying a large part of the peripheral region should be reduced. However, as the dimension of the MOS capacitor is decreased, the capacitance thereof is also reduced. Therefore, so as to form the reservoir capacitor having a large capacity while having a minute dimension, the reservoir capacitor having a structure similar to the cell capacitor formed in the cell region is fabricated in the peripheral region. In particular, a 3-dimensional structure used to form the cell capacitor in the cell region may be applied to the reservoir capacitor in the peripheral region, and thus the reservoir capacitor having capacitance about 17 to 18 times higher than that of the MOS capacitor can be fabricated in the same dimension of the peripheral region.
FIG. 1 is a sectional view illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device is typically divided into a cell region 10, a core area 20, a peripheral region 30 and a fringe area 40. Hereinafter, respective areas will be described in more detail.
First, in the cell region 10, an isolation layer 104 for defining an active region 102 is formed in a semiconductor substrate and a plurality of gate patterns 106 are formed on the active region 102. Landing plugs 107 are formed between the gate patterns 106, and a bit line contact 108 and a storage node contact 109 are formed on the landing plugs 107. The bit line contact 108 is connected to a bit line 110. A lower electrode 112 of a cell capacitor is formed to be connected to the storage node contact 109 formed over the active region 102, wherein the lower electrode 112 is of a pillar type and disposed over the bit line 110. An upper electrode 114 of the cell capacitor is formed over the lower electrode 112, and a dielectric layer (not shown) of the cell capacitor is formed between the lower and upper electrodes 112 and 114. A plurality of metal wires 120 and 122 and a plurality of contacts 116 and 118 are formed over the capacitor.
The core area 20 includes a sense amplifier and a switch which are comprised of a plurality of transistors formed on the active region 102 like in the cell region 10. The core area 20 does not include a capacitor for storing data, but includes a transistor and contacts 116 and 118 for connecting a plurality of metal wires 120 and 122 which are formed at the same height as in the cell region 10.
The peripheral region 30 includes a pad 134 for inputting/outputting data and signals, and various wires. In addition, the peripheral region 30 includes reservoir capacitors 130 and 132 for a stable operation. The reservoir capacitors 130 and 132 includes the second reservoir capacitor 130 having an electrode of a pillar type like the capacitor formed in the cell region 10 and the first reservoir capacitor 132 which uses a MOS transistor formed in the active region as a capacitor, wherein the MOS transistor is of a planar type. The peripheral region 30 further includes a fuse 136 and a guard ring 138.
A plurality of elements are very densely disposed in the cell region 10, but there are many empty spaces between several elements in the peripheral region 30 compared with the cell region 10. Among elements formed in the peripheral region 30, the reservoir capacitors 130 and 132 occupy a relatively large area and dimension. The area occupied by the reservoir capacitors 130 and 132 is about 10% of the total chip area of the semiconductor memory device.
As an integration degree of semiconductor memory devices get higher, an area assigned to reservoir capacitors gets smaller. If the minimal size of the plurality of elements and the minimal space between the elements included in the semiconductor memory device is maintained, to overcome the limit of a fabrication margin and enhance the operation stability, the area where the reservoir capacitors are to be formed may be inevitably diminished.
If an area assigned to the reservoir capacitor is sufficient, a semiconductor memory device may use a MOS transistor as a reservoir capacitor. However, as the integration degree of the semiconductor memory device become higher, it is difficult to ensure the capacitance of the reservoir capacitor by using the MOS transistor. Therefore, the reservoir capacitor is formed to have a structure similar to that of the cell capacitor so that the capacitance can be ensured even in a narrow area. Recently, as the integration degree of the semiconductor memory device gets much higher, the area assigned to the reservoir capacitor is further diminished. Thereafter, it is very difficult to ensure the capacitance of the reservoir capacitor and the operation stability of the semiconductor memory device. Therefore, a new technique for fabricating a reservoir capacitor is needed to prevent the capacitance of the reservoir capacitor from being reduced although the integration degree of the semiconductor memory device becomes higher.